Wang, Nan
Lyles College of Engineering
| Wang, N., Tankasali, T., & Murkumbi, O. (2017). Efficient reversible arithmetic logic units designs and evaluation. Presented at 2nd International Conference on Electronics Engineering and Informatics (ICEEI 2017), Beijing, China. |
| Wang, N., Pasumathi, K., & Chaturvedi, S. (2017). Implementation and performance analysis of two error detection and correction techniques: CRC and hamming code. Presented at IEEE Wireless Telecommunication Symposium (WTS 2017), Chicago, IL. |
| Wang, N., Mueller, E., & Valencia, P. (2017). Zigzag: an efficient deterministic network-on-chip routing algorithm design. Presented at The 8th IEEE Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON 2017), Vancouver, Canada. |
| Wang, N., & Mueller, E. (2017). Network-on-chip communication architecture: routing algorithm designs. Presented at 38th Central California Research Symposium, Fresno, CA. |
| Wang, N., Kumar, R., & Basavaraj, R. (2017). Implementation and performance evaluation of pipelining mechanism in 32-bit MIPS architecture. Presented at The 2nd International Conference on Electronics Engineering and Informatics (ICEEI 2017), Beijing, China. |
Wang, N., Bai, Y., & Mai, Y.
(2017).
Performance comparison and evaluation of the routing protocols for MANETs using NS3.
Journal of Electrical Engineering. 5(4).
|
| Wang, N., Bai, Y., & Mai, Y. (2017). Performance evaluation and analysis of the proactive and reactive routing protocols for MANETs. Presented at IEEE Wireless Telecommunications Symposium (WTS 2017), Chicago, IL. |
| Wang, N., & Valencia, P. (2016). Traffic allocation: an efficient adaptive network-on-chip router algorithm design. Presented at 2016 2nd IEEE International Conference on Computer and Communications, Chengdu, China. |
| Wang, N., Zhao, P., McNeely, J., Kuang, W., & Wang, Z.
(2011).
Design of sequential elements for low power clocking system.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19(5),
914-918.
|
| Wang, N.
(2010).
PMCNOC: a pipelining multi-channel central caching network-on-chip communication architecture design.
Journal of Signal and Processing. 60(3),
315-331.
|
| Wang, N.,
Zhao, P.,
Downey, L.,
McNeely, J.,
Bayoumi, M.,
Golconda, P.,
... Kuang, W.
(2009).
Low-power clocked-pseudo-NMOS flip-flop for level conversion in dual supply systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 17(9),
1196-1202.
|
| Wang, N., Bayoumi, M., & Sanusi, A. (2008). Guaranteeing QoS with the pipelined multi-channel central caching NoC communication architecture. Presented at 2008 IEEE International SOC Conference, Newport Beach, CA. |
| Wang, N., & Bayoumi, M.
(2007).
System-on-chip communication architecture: dynamic parallel fraction control bus design and test methodologies.
IET Computers & Digital Techniques. 1(1),
1-8.
|
| Wang, N., Sanusi, A., Zhao, P., Mohamed, S., & Bayoumi, M. (2007). A multi-channel central caching network-on-chip communication architecture design. Presented at 2007 IEEE Workshop on Signal Processing Systems, Shanghai, China. |
| Wang, N., & Bayoumi, M. (2006). DPCI: an efficient scalable system-on-chip communication architecture. Presented at IP-Soc 2006: IP-SOC-IOT Conference & Exhibition, Grenoble, France. |
| Wang, N., Sanusi, A., & Bayoumi, M. (2006). CTCNOC: a central caching network-on-chip communication architecture design. Presented at IP-Soc 2006: IP-SOC-IOT Conference & Exhibition, Grenoble, France. |
| Wang, N., & Bayoumi, M. (2005). Dynamic fraction control bus: new SOC on-chip communication architecture design. Presented at IEEE International System-on-Chip Conference (SOCC), Washington, DC. |
| Wang, N., & Xu, J.
(1997).
MSE self-adaptive quantizer of first-class signals.
Journal of Telemetry, Tracking, and Command.
|
